1. Field of the Invention
The present invention relates to a silicon-on-insulator (SOI)-type semiconductor device.
2. Description of the Related Art
Portable electronic apparatus have required less power dissipation, and therefore, the a power supply voltage for integrated circuits in such apparatuses has been lowered. However, the lower the power supply voltage, the lower the operation speed.
For example, in an N-channel MOS gate circuit, the operation speed is approximately in proportion to EQU (V.sub.DD -V.sub.th).sup.2
where V.sub.DD is a power supply voltage; and
V.sub.th is a threshold voltage of a MOS transistor.
Therefore, when the power supply voltage is lowered without changing the threshold voltage, the operation speed is rapidly lowered. Conversely, when the power supply voltage is lowered simultaneously with the lowering of the threshold voltage, a sub threshold current is increased so that the power dissipation in a standby mode is increased.
In a first prior art semiconductor device, in an active mode, a power supply voltage V.sub.DD is applied to back gates of P-channel MOS transistors, and a ground voltage is applied to back gates of N-channel MOS transistors, so as to increase the operation speed with the increase of the power dissipation. Conversely, in a standby mode, a voltage higher than the power supply voltage is applied to the back gates of the P-channel MOS transistors, and a negative voltage is applied to the back gates of the N-channel MOS transistors. Therefore, the absolute values of threshold voltages of the P-channel MOS transistors and the N-channel MOS transistors are increased so as to reduce the power dissipation with the lowering of the operation speed (see JP-A-4-302897).
In the first prior art semiconductor device, however, since charge pump circuits are required to generate the voltage higher than the power supply voltage and the negative voltage in a standby mode, the effect of reduction of the power dissipation in the standby mode is compensated for by the power dissipation of the charge pump circuits. Thus, a substantial power reduction cannot be expected.
In a second prior art semiconductor device, in an active mode, a shallow negative voltage is applied to a back gate of an N-channel MOS transistor, so as to increase the operation speed with the increase of the power dissipation. Conversely, in a standby mode, a deep negative voltage is applied to the back gate of the N-channel MOS transistor, to raise the threshold voltage thereof, thus reducing the power dissipation with the lowering of the operation speed (see JP-A-60-10656).
Also, in the second prior art semiconductor device, since charge pump circuits are required to generate the shallow and deep negative voltages, the effect of reduction of the power dissipation in the standby mode is compensated for by the power dissipation of the charge pump circuits. Thus, a substantial power reduction cannot be also expected.
In a third prior art semiconductor, in an active mode, a voltage lower than a power supply voltage is applied to a back gate of a P-channel MOS transistor, and a positive voltage is applied to a back gate of an N-channel MOS transistor, so as to increase the operation speed with the increase of the power dissipation. Conversely, in a standby mode, the power supply voltage is applied to the back gates of the P-channel MOS transistors, and the ground voltage is applied to the back gates of the N-channel MOS transistors. Therefore, the absolute values of threshold voltages of the P-channel MOS transistors and the N-channel MOS transistors are increased so as to reduce the power dissipation with the lowering of the operation speed (see JP-A-6-21443).
Thus, in the above-described third prior art semiconductor device, since charge pump circuits are unnecessary, the power dissipation can be expected.
However, when the above-descrived third prior art semiconductor device is applied to a conventional CMOS device, the following problems occur. First, a short-circuit is generated between a well and a substrate, and accordingly, it is impossible to control the threshold voltages. Also, in a large scale semiconductor device, a large parasitic capacitance is generated between the well and the substrate. Therefore, when the control is transferred from a standby mode to an active mode or vice versa, the large parasitic capacitance needs to be charged or discharged, which requires a long transition time. This will be also explained later in detail.